1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device having an error check and correcting function.
2. Description of the Prior Art
Recently, in a semiconductor memory device, soft errors with high integration density has become a problem. In addition, malfunctions due to, for example, destruction of a cell caused by a cell structure occur by repeatedly writing and erasing data. In order to solve the problems, a semiconductor memory device comprising an error check and correcting (referred to as ECC hereinafter) function on the same semiconductor substrate is disclosed in, for example, "64K Bit EEPROM Containing ECC", Technical Report of Institute of Electronics and Communication Engineers of Japan, Vol. 86, No. 1.
FIG. 1 is a block diagram showing an example of a structure of a conventional EEPROM (Electrically Erasable and Programmable Read Only Memory) comprising an ECC circuit.
In FIG. 1, a memory cell array 1 includes a memory cell array 1a for storing main data and a memory cell array 1b for storing check data. In the memory cell array 1, a plurality of word lines and a plurality of bit lines are arranged intersecting with each other, memory cells being provided at intersections thereof. In FIG. 1, there are typically shown only a single word line WL, a single bit line BL and a single memory cell 101 provided at intersections thereof.
An X address buffer 2 detects, waveform-shapes and amplifies input signals X0 to Xn, to apply the same to an X decoder 3. The X decoder 3 is responsive to the input signals X0 to Xn applied from the X address buffer 2 for selecting any of the word lines in the memory cell array 1a for storing main data. On the other hand, a Y address buffer 4 detects, waveform-shapes and amplifies input signals Y0 to Ym, to apply the same to a Y decoder 5. The Y decoder 5 is responsive to the input signals Y0 to Ym applied from the Y address buffer 4 for selecting any of the bit lines in the memory cell array 1a for storing main data through a Y gate circuit 6. Data D0 to D7 are inputted and outputted to and from a data pin 7. At the time of writing data, the data D0 to D7 applied to the data pin 7 are detected, waveform-shaped and amplified by an input buffer 8. The data D0 to D7 outputted from the input buffer 8 are transmitted to the selected bit lines in the memory cell array 1a for storing main data through the Y gate circuit 6, and further latched in a column latch high voltage switch 18. In addition, the data D0 to D7 outputted from the input buffer 8 are also applied to a check bit generating circuit 9. The check bit generating circuit 9 checks the data D0 to D7 and generates check bit data P1 to P4 of four bits. The check bit data P1 to P4 outputted from the check bit generating circuit 9 are transmitted to the bit lines in the memory cell array 1b for storing check data, and further latched in the column latch high voltage switch 18.
At the time of reading out data, a sense amplifier 10 detects and amplifiers the data D0 to D7 and the check bit data P1 to P4 read out from the memory cell array 1 through the Y gate circuit 6. An ECC circuit 11 checks the data D0 to D7 read out through the sense amplifier 10 in response to the check bit data P1 to P4, to automatically detect and correct a failure bit of one bit when the same is generated. The data D0 to D7 outputted from the ECC circuit 11 are outputted to the exterior from the data pin 7 through an output buffer 12.
A control signal buffer 13, a read/write control circuit 14, an erase/program control circuit 15, a high voltage generating circuit 16 and a read control circuit 17 are responsive to a chip enable signal CE, an output enable signal OE, a write enable signal WE and the like which are externally applied for controlling reading, writing or outputting of data in the memory cell array 1 or bringing a chip to the operating state or the standby state. The column latch high voltage switch 18 latches the data D0 to D7 and the check bit data P1 to P4 as inputted, and applies a high voltage to the bit line BL at the time of programming while applying a high voltage to a control gate line CGL at the time of erasing. A word line high voltage switch 19 applies a high voltage to the word line WL at the time of programming and erasing.
FIG. 2 is a cross-sectional view of a memory cell 101 included in the EEPROM shown in FIG. 1. In FIG. 2, the memory cell 101 comprises a selecting transistor 102 and a memory transistor 103. The selecting transistor 102 includes an N.sup.+ layer 104 and an N.sup.+ layer 105 formed in a P type silicon substrate 100 and a gate electorode 106. The memory transistor 103 includes the N.sup.+ layer 105 and an N.sup.+ layer 107 formed in the P type silicon substrate 100, a floating gate 108 and a control gate 109. As described above, a gate of the memory transistor 103 has a two-layer structure covered with an insulating layer (not shown). The N.sup.+ layer 105 becomes a source of the selecting transistor 102 and a drain of the memory transistor 103. Binary data "0" and "1" are stored in the memory cell 101 corresponding to the change in threshold voltage caused by storing positive or negative charges in the floating gate 108. A part of an insulating layer between the floating gate 108 and the N.sup.+ layer 105 is formed of a very thin oxide film. The N.sup.+ layer 104 in the selecting transistor 102 is connected to a bit line BL, and the gate electrode 106 therein is connected to a word line WL. The control gate 109 in the memory transistor 103 is connected to a control gate line CGL.
FIG. 3 is a circuit diagram showing a structure of the check bit generating circuit 9 included in the EEPROM shown in FIG. 1. As shown in FIG. 3, the check bit generating circuit 9 comprises four exclusive logical sum circuits (referred to as EXOR circuits hereinafter) 91 to 94. Four or five of the data D0 to D7 are applied to four or five input terminals of each of the EXOR circuits 91 to 94. Each of the EXOR circuits 91 to 94 outputs "0" when the number of data "1" as inputted is an even number while outputting "1" when the number is an odd number. The check bit data P1 to P4 are outputted from the four EXOR circuits 91 to 94, respectively.
FIG. 4 is a circuit diagram showing a structure of the ECC circuit 11 included in the EEPROM shown in FIG. 1. As shown in FIG. 4, the ECC circuit 11 comprises EXOR circuits 121 to 124, inverters 131 to 134, logical product circuits (referred to as AND circuits hereinafter) 140 to 147 and EXOR circuits 150 to 157. Four or five of the data D0 to D7 and one of the check bit data P1 to P4 are applied to five or six input terminals of each of the EXOR circuits 121 to 124. Outputs M1 to M4 are obtained by the four EXOR circuits 121 to 124, respectively. In addition, the outputs M1 to M4 are inverted by the inverters 131 to 134, respectively, to obtain inverted outputs M1 to M4 The output M1 or the inverted output M1, the output M2 or the inverted output M2, the output M3 or the inverted output M3 and the output M4 or the inverted output M4 are applied to four input terminals of each of the AND circuits 140 to 147, respectively. An output of each of the AND circuits 140 to 147 is applied to one input terminal of corresponding one of the EXOR circuits 150 to 157. The EXOR circuits 150 to 157 have their other input terminals receiving the data D0 to D7, respectively. Outputs D.sub.0a to D.sub.7a are obtained by the EXOR circuits 150 to 157, respectively.
The EXOR circuits 121 to 124 check bits as inputted and check bits. In addition, the EXOR circuits 150 to 157 correct bit errors.
Description is now made on an operation of the EEPROM shown in FIG. 1 in the order of (1) erasing and programming operations in the memory cell, (2) a writing operation of data, and (3) a reading operation of data.
(1) Erasing and programming operations in the memory cell
In the erasing operation and the programming operation, electrons are tunneled through a thin oxide film between the floating gate 108 and the N.sup.+ layer 105 (in FIG. 2).
The erasing operation means that a threshold voltage of the memory transistor 103 is shifted higher by injecting electrons into the floating gate 108, to store data "1" in the memory cell 101. The erasing operation is performed by bringing the bit line BL to the ground potential and applying a high voltage to the word line WL and the control gate line CGL.
The programming operation means that a threshold voltage of the memory transistor 103 is shifted lower by emitting electrons from the floating gate 108, to store data "0" in the memory cell 101. The programming operation is performed by bringing the control gate line CGL to the ground potential and applying a high voltage to the word line WL and the bit line BL.
(2) Writing operation of data
In FIG. 1, when the chip enable signal CE and the write enable signal WE are first inputted, there is formed a line of the control signal buffer 13, the read/write control circuit 14, the erase/program control circuit 15 and the high voltage generating circuit 16.
A word line WL is selected in response to signals inputted through the X address buffer 2 and the X decoder3, while bit lines BL are selected in response to signals inputted through the Y address buffer 4, the Y decoder 5 and the Y gate circuit 6. When the data D0 to D7 are inputted through the data pin 7, the data are transmitted to the selected bit lines BL in the memory cell array 1a for storing main data through the input buffer 8 and the Y gate circuit 6, and further latched in the column latch high voltage switch 18.
On the other hand, the data D0 to D7 outputted from the input buffer 8 are also inputted to the check bit generating circuit 9, where the check bit data P1 to P4 of four bits are generated. The check bit data P1 to P4 are transmitted to the bit lines BL in the memory cell array 1b for storing check data through the Y gate circuit 6, and further latched in the column latch high voltage switch 18.
The check bit data P1 to P4 are generated by the EXOR circuits 91 to 94 to which four or five data out of the data D0 to D7 are inputted (see FIG. 3). For example, if the inputted data D0 to D7 are (0,1,0,1,0,1,0,1, ) in that order, the check bit data P1 to P4 are (0,1,1,1) in that order. When latch of addresses and data are completed, a high voltage is supplied to the column latch high voltage switch 18 and the word line high voltage switch 19 by the high voltage generating circuit 16, so that the memory cell array 1 is activated. Consequently, data is written to a desired memory transistor 103 in response to the erasing/programming operation in the above described memory cell.
(3) Reading operation of data
When the chip enable signal CE and the output enable signal OE are first inputted, the control signal buffer 13, the read/write control circuit 14, the read control circuit 17, the sense amplifier 10 and the output buffer 12 are activated.
Thereafter, a word line WL is selected in response to signals inputted through the X address buffer 2 and the X decoder 3, and bit lines BL are selected in response to signals inputted through the Y address buffer 4, the Y decoder 5 and the Y gate circuit 6. Consequently, the data D0 to D7 and the check bit data P1 to P4 in the memory cells at intersections of the selected word line WL and the selected bit lines BL are applied to the ECC circuit 11 through the bit lines BL, the Y gate circuit 6 and the sense amplifier 10.
More specifically, the data D0 to D7 and the check bit data P1 to P4 are first inputted to the EXOR circuits 121 to 124 in the same combination as that selected in the check bit generating circuit 9 at the time of writing (see FIG. 4). The check bit data P1 to P4 are previously determined such that the number of "1" in corresponding data (for example, D0, D1, D2 and D3 in the case of P1) becomes an even number. Thus, if a failure does not occur in the memory transistor 103, all the outputs M1 to M4 from the EXOR circuits 121 to 124 attain an "L" level, and all the inverted outputs M1 to M4 from the inverters 131 to 134 attain an "H" level. Consequently, all the outputs of the AND circuits 140 to 147 in the next stage attain the "L" level. Eventually, all the input data D0 to D7 become the outputs D.sub.0a to D.sub.7a of the EXOR circuits 150 to 157 in the final stage without any modification, respectively.
Let's consider a case in which one of the memory transistors 103 fails, so that one bit, for example, the data D3, which is essentially to be "1" but erroneously become "0", is inputted to the ECC circuit 11.
In this case, data inputted to the EXOR circuit 121 becomes (0, 1, 0, 0, 0) and data inputted to the EXOR circuit 124 become (1, 0, 0, 0, 1, 1), so that outputs M1 and M4 attain the "H" level and the inverted outputs M1 and M4 attain the "L" level. Both the outputs M2 and M3 attain the "L" level because the data D3 is not inputted. Thus, data inputted to the AND circuit 143 out of the AND circuits 140 to 147 in the next stage become (1, 1, 1, 1,). Consequently, an output of the AND circuit 143 attains the "H" level while outputs of the other AND circuits 140 to 142 and 144 to 147 all attain the "L" level. If the outputs of the AND circuits 140 to 147 are at the "L" level, the level in phase with the other input signal, i.e., the data D0 to D7 is outputted from the EXOR circuits 150 to 157 in the next stage.
In this case, since the outputs of all the AND circuits 140 to 142 and 144 to 147 excluding the AND circuit 143 are at the "L" level, the inputted data D0 to D2 and D4 to D7 become the outputs D.sub.0a to D.sub.2a and D.sub.4a to D.sub.7a without any modification. On the other hand, since the output of the AND circuit 143 is at the "H" level, the output D.sub.3a becomes data obtained by inverting the other data D3 inputted to the EXOR circuit 153.
In the above described manner, the data D3 in the faulty memory transistor 103 is checked and corrected in the ECC circuit 11. Consequently, the same data D0 to D7 as that as inputted are outputted from the data pin 7 through the output buffer circuit 12.
Although description was made on a case in which a bit error occurs in one of the data D0 to D7 out of the 12-bit data (D0 to D7 and P1 to P4) simultaneously written in the memory cell array 1, a bit error may occur in one of the check bit data P1 to P4, in which case the normal data D0 to D7 are outputted from the ECC circuit 11.
The conventional EEPROM has the above described structure. Thus, if a bit failure in the same byte is one bit or less, the bit failure is checked and corrected in the ECC circuit 11, and thus remedied. However, the EEPROM cannot understand how many bytes in one chip are remedied in the ECC circuit.
Let's consider an EEPROM having storage capacity of 64 kilobits, i.e., 8192 bytes. Assuming that the above described ECC circuit is contained in the EEPROM, bit failures may be checked and corrected in any of the following cases: (1) the number of faulty memory transistors is 8192, (2) the number is 10 and (3) the number is 0. Therefore, the EEPROM in which the bit failures are detected and corrected can be employed as normal one. However, the EEPROM cannot understand how many bytes in one chip are remedied by the ECC circuit.
In the above described cases, the EEPROM is apparently normal. However, in the case (1), a failure of one additional memory transistor is not thereafter permitted. On the other hand, in the case (2), failures up to 8182 memory transistors may be permitted. In addition, in the case (3), failures up to 8192 memory transistors may be permitted. Thus, in the cases, there occurs a large difference in reliability of the EEPROM.
However, if writing/erasing of data to/from the memory transistor is repeated, the destruction thereof is liable to occur. Under the present condition, this cannot be avoided to some degree from the point of view of the structure of the memory transistor. If the reliability of the EEPROM can be evaluated by understanding the states such as the above described cases (1) to (3), it can be determined whether or not the EPROM can be continuously used. In addition, substantially effective information is obtained so as to make an improvement in the design or the manufacturing process.